The present invention relates to methods and apparatus for mapping a macro-instruction to a microcode instruction memory.
Many computers today execute instructions by storing a number of microcode instructions for each macro-instruction in a microcode memory. The microcode instructions are then executed for the particular macro-instruction to implement the macro-instruction. A typical method is shown in FIG. 1, where a macroinstruction is placed into an operation code instruction register 10. The instruction in register 10 is then decoded by a mapping circuit 12 to produce an address which is provided to a microcode memory 14. This address will be the address of the first microinstruction in a series of micro-instructions to implement the particular macro-instruction. The remaining micro-instructions are obtained by incrementing the first micro-instruction address 16 by one after that micro-instruction is executed to produce successive micro-instructions 18, 20 and 22 for the macroinstruction.
In one implementation, each macro-instruction is allocated a fixed number of micro-instructions. If this fixed number is four, for instance, then any macro-instruction which requires more than four microinstructions must include a jump in the last microinstruction to a separate area of the microcode memory 14. A jump is undesirable because it places additional requirements on the microcode in terms of time or space. To do a jump, a jump address must be specified, and this requires space. In addition, another clock cycle may be required for a jump. To avoid the requirement of a jump, enough space can be allocated to accommodate the largest macro-instruction, but this results in a large number of wasted memory spaces for macro-instructions which require less than the maximum number of micro-instructions. Alternately, the microcode memory could be divided into groups of different fixed sizes with the sizes varying by a power of two (i.e., groups of four, eight, sixteen, etc.). Thus, a short macro-instruction could be allocated for microcode addresses 16-22 as shown in FIG. 1, while a longer macro-instruction can be allocated eight microcode memory addresses starting at location 23 as shown in FIG. 1. Numbers of microcode addresses which are not a power of two cannot be accommodated without requiring additional circuitry for mapping circuit 12. A power of two implementation can be done simply by blocking out unwanted bits to result in a higher number.
Map circuit 12 could be implemented to accommodate a particular instruction set so that the number of micro-instruction addresses allocated to a particular macro-instruction varies. This would require that either the instruction set be fixed at the time the map is fixed or that the map circuit itself be programmable.